1. Field of the Invention
The present invention relates to programmable waveform generators and, in particular, to waveforms which are derived from a periodic reference signal.
2. Description of the Related Art
The events occurring within many integrated circuits are referenced to a periodic clock signal. Frequently, it is desirable to synchronize the events occurring within several integrated circuits so that related events can occur at the same time. One method of synchronizing interchip timing is to distribute the same clock signal to each of the integrated circuits.
In a typical application, however, it is unlikely that the same clock signal will synchronously trigger events in several integrated circuits because of differing electrical path lengths, capacitive variations, and temperature variations. Because of these differences, a simultaneous event may be triggered in one integrated circuit several nanoseconds before it's corresponding event is triggered in a second integrated circuit.
The solution to this problem has been to delay the clock signals sent to the earlier triggering integrated circuits. For example, if a periodic clock signal triggers a first integrated circuit in five nanoseconds and a second integrated circuit in six nanoseconds, substantial synchronization can be achieved by passing the clock signal transmitted to the first integrated circuit through a discrete component which has a one nanosecond delay. Thus, the periodic clock signal may trigger events within the first and second integrated circuits at approximately six nanoseconds.
Often, however, it is not practical to implement the above solution using discrete components because the specified delay tolerance is too large. The process of individually testing each component to determine the actual delay time and then matching it to a delay circuit makes this approach unsuitable for high volume manufacturing procedures. Additionally, discrete components are also unsuited because of the large amount of board space they require.
A second implementation of this solution, as discussed in "Design of PLL-Based Clock Generation Circuits", J. Solid-State Circuits, Vol. SC-22, No. 2, April 1987, utilizes a voltage controlled oscillator, a nine gate ring oscillator, and AND gates configured as a phase locked loop. By logically ANDing the outputs from the ring oscillator, four clock signals, with approximately a 40 nanosecond phase delay between clock signals, were produced.
A third implementation, as discussed in Computer Design, Pg. 40, Sep. 1, 1990, uses a 160 megahertz (MHz) gallium arsenide voltage controlled oscillator and a digital delay line configured as a phase locked loop, to produce clock signals with approximately a 2 ns phase delay between different clock signals.
Although both implementations provide methods for achieving phase delays, the rapidly increasing speeds that computer systems may operate under make it desirable to reduce the phase shift resolution below 2 ns. In addition, one problem with the third implementation is that gallium arsenide fabrication is much more expensive than standard silicon processing. Thus, there is a need to produce a clock signal, using silicon fabrication, which tracks the reference clock signal with a forward or backward phase shift resolution of less than 2 ns.
In addition to phase shifting a clock signal to simultaneously trigger events in multiple integrated circuits, it is frequently desirable to produce frequency multiplied clock signals. One example of where frequency multiplication is desirable is interboard clock signal transmission. For example, if a 40 MHz signal is to be synchronously used on different boards, significant capacitive problems may be avoided if a 10 or 20 MHz signal is first transmitted to the outlying boards and then multiplied back up to the original 40 MHz signal frequency.
One method of multiplying a frequency, as discussed in Computer Design, Pg. 40, Sep. 1, 1990, has been to use a voltage controlled oscillator and a counter chain configured as a phase locked loop. In this implementation, the frequency of an original clock signal is divided in half and then transmitted to a second board. At the second board, the voltage controlled oscillator produces the original clock signal frequency. The signal at the second board is then synchronized to the first board by dividing the signal at the second board and using the phase locked loop to track the two divided signals.
A variation of the above frequency division method, as discussed in Computer Design, Pg. 40, Sep. 1, 1990, has been to use a 160 MHz gallium arsenide voltage controlled oscillator. By using a voltage controlled oscillator which runs at such a high frequency, the 160 MHz signal may be divided down several times to produce frequencies which are up to eight times the input frequency. As stated above, one problem with gallium arsenide is the increased cost of using this medium.
Thus, there is a need to provide a method and apparatus for forming a clock signal in a manner that would solve the above identified problems.